One of the most popular types of analog-to-digital converters for high-speed use is the parallel, or flash, converter. A good reference for general background information on flash converters is D. H. Sheingold, (ed.), The Engineering Staff of Analog Devices, Inc., Analog-Digital Conversion Handbook (3rd ed.), Prentiss-Hall, Englewood Cliffs, N.J., at pp. 420-427, which is incorporated by reference herein. In general, the input node of a flash ADC is connected in parallel to the inputs of a large number of emitter-followers, each of which drives a comparator. The number of emitter-followers, N, is 2.sup.n -1, where n is the number of bits in the digital output.
The dynamic performance of flash converters is usually limited by harmonic distortion at high frequencies. This harmonic distortion is largely attributable to the fact that the parallel emitter followers present a substantial non-linear, voltage-dependent capacitance at the input node, which is driven by a source having a non-zero output impedance. Referring to FIG. 1, a typical input stage 10.sub.i is shown (where i varies from 0 to 2.sup.n -1). Of course, there are 2.sup.n -1 such stages connected in parallel at input node 12. The input stage 10.sub.i comprises a first emitter-follower transistor 14 driven by the input signal; a second emitter-follower transistor 16 which senses a voltage on a resistive ladder 18; and a comparator formed of a differential amplifier pair 22A, 22B. The transistors are biased by current sources 24, 26, and 28. The collectors of transistors 14 and 16 are connected at node 36 ground or a fixed voltage source. Node 12 is assumed to be driven by a source 32, having an output impedance 34 of value R.sub.o. The input impedance of the converter, at node 12, includes a large capacitive component attributable largely to the collector junction capacitances (Cbc's) of the input emitter-follower transistors 14. This junction capacitance is non-linear and voltage-dependent. An error voltage is therefore created at the input, as the current for charging and discharging the input capacitance flows through the driving source impedance 34.
An obvious solution to this problem is to use an amplifier or buffer of very low output impedance to drive the flash converter. This solution is not effective, however, for very high-speed, high-resolution (i.e., more than about 6 bits) converters. First, there is a lack of commercially available amplifiers or buffers with distortion levels low enough to prevent the amplifier from limiting the system performance. Secondly, due to the capacitive input of the converter, a series resistance generally must be placed between the driving source (including such an amplifier) and the converter, in order to maintain stability. This series resistance results in exactly the problem described above.
Another approach is to bias the emitter-follower transistors to a voltage more positive than that required for the input range, so as to operate the transistors in a range where the voltage dependency of the input capacitance is reduced. This approach does result in a reduction of harmonic distortion caused by junction capacitance changes, but it does not eliminate such distortion.
Accordingly, it is an object of the present invention to provide an input circuit for a flash analog-to-digital converter which substantially eliminates harmonic distortion at high input frequencies.